Semiconductor memory device

ABSTRACT

A semiconductor memory device includes: a memory cell array including memory strings, one of the memory strings including memory cells; word lines commonly connected to the memory strings; and a controller configured to execute a write operation and a read operation on a page, the page being stored in memory cells connected to one of the word lines. The controller is configured to measure a cell current flowing in the memory string, and adjust a write voltage applied to a word line, based on a result of the cell current.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2014-180577, filed Sep. 4, 2014, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor memorydevice.

BACKGROUND

There is known a NAND flash memory in which memory cells arethree-dimensionally arranged.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a memory system according to a firstembodiment;

FIG. 2 is a block diagram of a NAND flash memory according to the firstembodiment;

FIG. 3 is a circuit diagram of one block included in a memory cellarray;

FIG. 4 is a cross-sectional view of a partial region of the memory cellarray;

FIG. 5 is a view for explaining a threshold distribution of a memorycell transistor;

FIG. 6 is a block diagram of a sense amplifier unit and a page buffer;

FIG. 7 is a circuit diagram of a main part of a sense amplifier and acell current measuring circuit;

FIG. 8 is a timing chart of a lower page program operation including acell current measuring operation according to the first embodiment;

FIG. 9 is a graph for explaining an example of the relationship betweena signal VBLC and a cell current iCELL;

FIG. 10 is a view illustrating a relationship between a signal VBL_DACand operation parameters;

FIG. 11 is a view illustrating another example of the relationshipbetween the signal VBL_DAC and operation parameters;

FIG. 12 is a timing chart of an erase operation according to the firstembodiment;

FIG. 13 is a flowchart of a lower page program operation according tothe first embodiment;

FIG. 14 is a view for explaining a redundancy area for writing flagdata;

FIG. 15 illustrates a voltage waveform of a voltage which is applied toa selected word line according to the first embodiment;

FIGS. 16A to 16D are a view for explaining an example of an initialprogram voltage and a step-up voltage included in first to fourthprogram parameter sets;

FIG. 17 is a flowchart of an upper page program operation according tothe first embodiment;

FIG. 18 is a timing chart of the upper page program operation accordingto the first embodiment;

FIG. 19 is a timing chart of a read operation according to the firstembodiment;

FIG. 20 is a cross-sectional view for explaining areas of a NAND string;

FIG. 21 is a view illustrating the relationship between the signalVBL_DAC and erase parameter sets;

FIG. 22 is a block diagram illustrating, mainly, a memory cell arrayaccording to a second embodiment;

FIG. 23 is a timing chart of a data transfer operation according to thesecond embodiment;

FIG. 24 is a flowchart of a lower page program operation according tothe second embodiment;

FIG. 25 is a flowchart of an upper page program operation according tothe second embodiment;

FIG. 26 is a flowchart of a lower page read operation according toExample 1;

FIG. 27 is a timing chart of the lower page read operation according toExample 1;

FIG. 28 illustrates voltage waveforms in read operations according toExample 1;

FIG. 29 is a flowchart of an upper page read operation according toExample 1;

FIG. 30 is a view illustrating the relationship between a differencebetween flag data and a count value, on one hand, and read levels, onthe other hand;

FIG. 31 is a timing chart of a read operation according to Example 2;

FIG. 32 is a flowchart of a lower page read operation according toExample 3;

FIG. 33 illustrates voltage waveforms in the lower page read operationaccording to Example 3;

FIG. 34 is a timing chart illustrating a write operation of a memorycontroller and a NAND flash memory according to a third embodiment;

FIG. 35 is a flowchart illustrating the write operation of the memorycontroller and NAND flash memory according to the third embodiment;

FIG. 36 is a flowchart illustrating a read operation of the memorycontroller and NAND flash memory according to the third embodiment;

FIG. 37 is a flowchart illustrating a read operation following the readoperation in FIG. 36;

FIG. 38 is a timing chart illustrating a write operation of a memorycontroller and a NAND flash memory according to a fourth embodiment;

FIG. 39 is a flowchart illustrating the write operation of the memorycontroller and NAND flash memory according to the fourth embodiment; and

FIG. 40 is a flowchart illustrating a read operation of the memorycontroller and NAND flash memory according to the fourth embodiment.

DETAILED DESCRIPTION

In general, according to one embodiment, there is provided asemiconductor memory device comprising:

a memory cell array including memory strings, one of the memory stringsincluding memory cells;

word lines commonly connected to the memory strings; and

a controller configured to execute a write operation and a readoperation on a page, the page being stored in memory cells connected toone of the word lines,

wherein the controller is configured to

measure a cell current flowing in the memory string, and

adjust a write voltage applied to a word line, based on a result of thecell current.

Embodiments will now be described with reference to the accompanyingdrawings. The drawings are merely schematic or conceptual, and thedimensions and ratios in these drawings do not necessarily match theactuality. Several embodiments to be described below merely exemplifydevices and methods for embodying the technical concepts of the presentinvention, and the shapes, structures, layouts, and the like of thecomponents do not limit the technical concepts of the present invention.Note that in the following explanation, the same reference numeralsdenote elements having the same functions and arrangements, and arepetitive explanation will be made only when necessary.

A semiconductor memory device is a nonvolatile semiconductor memorywhich is capable of electrically rewriting data. In embodiments to bedescribed below, a NAND flash memory will be described as an example ofthe semiconductor memory device. In addition, a three-dimensionalmulti-stacked NAND flash memory, in which memory cells are stacked on asemiconductor substrate, will be described as an example of the NANDflash memory.

First Embodiment

[1-1] Configuration of Memory System

First, a description is given of a configuration of a memory systemincluding a semiconductor memory device according to the presentembodiment. FIG. 1 is a block diagram of a memory system 300 accordingto the embodiment. The memory system 300 includes a NAND flash memory100 and a memory controller 200. Examples of the memory system 300include a memory card such as an SD™ card, and an SSD (Solid StateDrive).

The NAND flash memory 100 includes a plurality of memory cells, andstores data nonvolatilely. The details of the configuration of the NANDflash memory will be described later.

Responding to an instruction from a host device 400, the memorycontroller 200 instructs the NAND flash memory 100 to execute write,read and erase. In addition, the memory controller 200 manages a memoryspace of the NAND flash memory 100. The memory controller 200 includes ahost interface circuit (Host I/F) 210, a CPU (Central Processing Unit)220, a ROM (Read Only Memory) 230, a RAM (Random Access Memory) 240, anECC (Error Checking and Correcting) circuit 250, and a NAND interfacecircuit (NAND I/F) 260.

The host interface circuit 210 is connected to the host device 400 via acontroller bus, and executes an interface process between the hostinterface circuit 210 and the host device 400. In addition, the hostinterface circuit 210 transmits/receives instructions and data to/fromthe host device 400.

The CPU 220 controls the operation of the entirety of the memorycontroller 200. For example, when the CPU 220 received a writeinstruction from the host device 400, the CPU 220 responds to the writeinstruction and issues a write instruction based on the NAND interface.The same applies to the cases of read and erase. In addition, the CPU220 executes various processes for managing the NAND flash memory 100,such as wear leveling.

The ROM 230 stores firmware, etc. which are used by the CPU 220. The RAM240 is used as a working area of the CPU 220, and stores firmware whichwas loaded from the ROM 230, and various tables which the CPU 220created. The RAM 240 is also used as a data buffer, and temporarilystores data which was sent from the host device 400, and data which wassent from the NAND flash memory 100.

The ECC circuit 250 generates, at a time of data write, an errorcorrection code for write data, adds the error correction code to thewrite data, and sends the write data with the error correction code tothe NAND interface 260. In addition, at a time of data read, the ECCcircuit 250 executes error check and correction for read data by usingthe error correction code included in the read data. Incidentally, theECC circuit 250 may be provided in the NAND interface circuit 260.

The NAND interface circuit 260 is connected to the NAND flash memory 100via a NAND bus, and executes an interface process between the NANDinterface circuit 260 and the NAND flash memory 100. In addition, theNAND interface circuit 260 transmits/receives instructions and datato/from the NAND flash memory 100.

[1-1-1] Configuration of NAND Flash Memory 100

Next, the configuration of the NAND flash memory 100 is described. FIG.2 is a block diagram of the NAND flash memory 100 according to theembodiment. The NAND flash memory 100 includes a memory cell array 111,a row decoder (R/D) 112, a sense amplifier unit 113, a page buffer 115,a column decoder 116, a driver 117, a voltage generator (charge pump)118, an input/output circuit 119, a control circuit 120, anaddress/command register 121, and a register 122.

The memory cell array 111 includes a plurality of blocks BLK. Each ofthe blocks BLK is a set of nonvolatile memory cells which are associatedwith word lines and bit lines, respectively. FIG. 2 illustrates, by wayof example, four blocks BLK0 to BLK3. The block BLK is an erase unit ofdata, and the data in the same block BLK are erased collectively. Eachof the blocks BLK includes a plurality of string units SU. Each of thestring units SU is a set of NAND strings 114, in each of which memorycells are connected in series. FIG. 2 illustrates, by way of example,four string units SU0 to SU3. Needless to say, the number of blocks BLKand the number of string units SU in one block BLK can arbitrarily beset.

The row decoder 112 receives a block address signal and a row addresssignal from the address/command register 121. Based on these signals,the row decoder 112 selects word lines in the corresponding block. Thecolumn decoder 116 receives a column address signal from theaddress/command register 121, and selects bit lines, based on the columnaddress signal.

At a time of data read, the sense amplifier unit 113 senses andamplifies data which was read to bit lines from the memory cells. Inaddition, at a time of data write, the sense amplifier unit 113transfers write data to memory cells. The read and write of data fromand to the memory cell array 111 are executed in units of a plurality ofmemory cells, and this unit becomes a page.

The page buffer 115 stores data in units of a page. At a time of dataread, the page buffer 115 temporarily stores data which was transferredfrom the sense amplifier unit 113 in units of a page, and seriallytransfers the data to the input/output circuit 119. In addition, at atime of data write, the page buffer 115 temporarily stores data whichwas serially transferred from the input/output circuit 119, andtransfers the data to the sense amplifier circuit 113 in units of apage.

The input/output circuit 119 transmits/receives various commands anddata to/from the memory controller 200 via the NAND bus. Theaddress/command register 121 receives commands and addresses from theinput/output circuit 119, and temporarily stores them.

The driver 117 supplies voltages, which are necessary for write, readand erase of data, to the row decoder 112, sense amplifier unit 113, anda source line control circuit (not shown). The voltages generated by thedriver 117 are applied to the memory cells (word lines, select gatelines, bit lines, and source lines) via the row decoder 112, senseamplifier unit 113 and source line control circuit. The voltagegenerator 118 boosts a power supply voltage which is supplied from theoutside, and supplies various voltages with the driver 117.

The register 122 temporarily stores, for example, at a time of power-on,management data which was read from a ROM fuse of the memory cell array111. In addition, the register 122 temporarily stores various data whichare necessary for the operation of the memory cell array 111. Theregister 122 is composed of, for example, an SRAM.

The control circuit 120 controls the operation of the entirety of theNAND flash memory 100.

[1-1-2] Configuration of Memory Cell Array 111

Next, the configuration of the memory cell array 111 is described. FIG.3 is a circuit diagram of one block BLK included in the memory cellarray 111.

The block BLK includes, for example, four string units SU0 to SU3. Eachof the string units SU includes a plurality of NAND strings 114.

Each of the NAND strings 114 includes, for example, eight memory celltransistors MT (MT0 to MT7), and select transistors ST1 and ST2.Incidentally, in the description below, the term “memory celltransistor” and term “memory cell” are identical in meaning. Each of thememory cell transistor MT includes a stacked gate including a controlgate and a charge storage layer, and stores data nonvolatilely. In themeantime, the number of memory cell transistors MT is not limited toeight, and may be 16, 32, 64 or 128. The number of memory celltransistors MT can arbitrarily be set. The memory cell transistor MT aredisposed such that the current paths of the transistors MT are connectedin series between the select transistors ST1, ST2. The current path ofthe memory cell transistor MT7 on one end side of this series connectionis connected to one end of the current path of the select transistorST1, and the current path of the memory cell transistor MT0 on the otherend side of this series connection is connected to one end of thecurrent path of the select transistor ST2.

The gates of the select transistors ST1 included in the string unit SU0are commonly connected to a select gate line SGD0, and select gate linesSGD1 to SGD3 are connected to the string units SU1 to SU3 in likemanner. The gates of select transistors ST2 in the same block BLK arecommonly connected to an identical select gate line SGS. The controlgates of the memory cell transistors MT0 to MT7 in the same block BLKare commonly connected to word lines WL0 to WL7. Incidentally, like theselect transistors ST1, the select transistors ST2 included in therespective string units SU may be connected to different select gatelines SGS0 to SGS3.

In addition, the other ends of the current paths of the selecttransistors ST1 of the NAND strings 114 of the same row, among the NANDstring 114 disposed in a matrix in the memory cell array 111, arecommonly connected to any one of bit lines BL0 to BL (L−1). (L−1) is anatural number of 1 or more. Specifically, the bit line BL commonlyconnects the NAND strings 114 among the blocks BLK. In addition, theother ends of the current paths of the select transistors ST2 arecommonly connected to a source line SL. The source line SL commonlyconnects the NAND strings 114, for example, between a plurality ofblocks.

As described above, the data of memory cell transistors MT in the sameblock BLK are erased collectively. On the other hand, data read/write iscollectively executed for the memory cell transistors MT, which arecommonly connected to any one of the word lines WL, in any one of thestring units SU of any one of the blocks BLK. This unit of dataread/write is called “page”.

Next, an example of a cross-sectional configuration of the memory cellarray 111 is described. FIG. 4 is a cross-sectional view of a partialregion of the memory cell array 111.

A wiring layer 20 functioning as the source line SL is formed above asemiconductor substrate (not shown). A conductive film 21 a functioningas the select gate line SGS is formed above the source line SL. Aplurality of conductive films 22 functioning as word lines WL are formedabove the conductive film 21 a. A conductive film 21 b functioning asthe select gate line SGD is formed above the conductive film 22.Inter-electrode insulation films for electrically isolating theconductive films 21 a, 21 b and 22 are formed between the conductivefilms 21 a, 21 b and 22.

In addition, a memory hole is formed in the conductive films 21 a, 21 band 22 and inter-electrode insulation films. The memory hole penetratesthe conductive films 21 a, 21 b and 22 and inter-electrode insulationfilms, and extends in a vertical direction (direction D3) to the surfaceof the semiconductor substrate. For example, due to fabrication steps,the diameter of the memory hole becomes greater in an upward direction.Furthermore, a difference between the diameter of a lower part of thememory hole and the diameter of an upper part of the memory hole becomeslarger as the length of the memory hole becomes larger.

In the memory hole formed in a region which becomes the selecttransistor ST2, a gate insulation film 23 a and a semiconductor layer 24a are successively formed, and a pillar structure including the gateinsulation film 23 a and semiconductor layer 24 a is formed. In thememory hole formed in a region which becomes the memory cell transistorMT, a block insulation film 25, a charge storage layer (insulation film)26, a gate insulation film 27 and a semiconductor layer 28 aresuccessively formed, and a pillar structure including these films andlayers is formed. In the memory hole formed in a region which becomesthe select transistor ST1, a gate insulation film 23 b and asemiconductor layer 24 b are successively formed, and a pillar structureincluding the gate insulation film 23 b and semiconductor layer 24 b isformed. The semiconductor layers 24 a, 28 and 24 b are a region whichfunctions as a current path of the NAND string 114, and in which achannel is formed when the memory cell transistors MT operates.

In this manner, in each NAND string 114, the select transistor ST2,memory cell transistors MT and select transistor ST1 are successivelystacked. A wiring layer 29 functioning as the bit line BL is formed onthe semiconductor layer 24 b. The bit line BL is formed to extend in adirection D1.

A plurality of the above-described structures are arranged in a depthdirection (direction D2) of FIG. 4, and the string unit SU is formed ofa set of NAND strings 114 which are arranged in the direction D2. Inaddition, the plural select gate lines SGD, plural select gate lines SGSand plural word lines WL included in the same string unit SU arecommonly connected, respectively.

In the meantime, as regards the configuration of the memory cell array111, the memory cell array 111 may have other configurations. Forexample, the configuration of the memory cell transistor 111 isdisclosed in U.S. patent application Ser. No. 12/407,403 filed on Mar.19, 2009, titled “Three dimensional stacked nonvolatile semiconductormemory”. In addition, the configurations of the memory cell transistor111 are disclosed in U.S. patent application Ser. No. 12/406,524 filedon Mar. 18, 2009, titled “Three dimensional stacked nonvolatilesemiconductor memory”; U.S. patent application Ser. No. 12/679,991 filedon Mar. 25, 2010, titled “Nonvolatile semiconductor memory device andmanufacturing method of the same”; and U.S. patent application Ser. No.12/532,030 filed on Mar. 23, 2009, titled “Semiconductor memory andmethod for manufacturing the same”. The entire contents of these patentapplications are incorporated herein by reference.

[1-1-3] Threshold Distribution of Memory Cell Transistor MT

Next, a description is given of an example of a threshold distribution(threshold voltage distribution) of the memory cell transistor MT. FIG.5 is a view for explaining the threshold distribution of the memory celltransistor MT.

For example, the memory cell transistor MT can store data of two bits inaccordance with thresholds thereof. Two-bit data, which are stored inthe memory cell transistor MT are, for example, “11”, “01”, “00”, and“10” in an order from the lowest threshold. As regards “11”, “01”, “00”,and “10”, the left-side numeral indicates an upper bit, and theright-side numeral indicates a lower bit. A write unit of lower-bit datais called “lower page”, and a write unit of upper-bit data is called“upper page”.

If lower page program is executed, a threshold distribution of an erasestate (“E” level) illustrated in part (a) of FIG. 5 changes to twothreshold distributions illustrated in part (b) of FIG. 5, namely athreshold distribution of an erase state (“E” level) and a thresholddistribution of a middle level (“LM” level). The “LM” level has a higherthreshold than a read level ARL. The “LM” level is programmed by using averify level ML2V which is slightly higher than the read level ARL, andthe “LM” level has a higher threshold than the verify level ML2V. The“E” level is associated with data “1”, and the “LM” level is associatedwith data “0”.

If upper page program is executed after the lower page program, the twothreshold distributions illustrated in part (b) of FIG. 5 change to fourthreshold distributions as illustrated in part (c) of FIG. 5. The memorycell transistor MT can take a threshold of any one of the “E” level, “A”level, “B” level and “C” level. The “E” level, “A” level, “B” level and“C” level are associated with data “11”, “01”, “00” and “10”,respectively.

The “E” level is a threshold in a state in which charge in the chargestorage layer is drawn out and the data is erased, and has, for example,a negative value. The “E” level is lower than a verify voltage EV. The“A” to “C” levels are thresholds in states in which charge is injectedin the charge storage layer, and have, for example, positive values. The“A” level has a threshold which is higher than the read level AR and islower than a read level BR. The “B” level has a threshold which ishigher than the read level BR and is lower than a read level CR. The “C”level has a threshold which is higher than the read level CR and islower than a voltage VREAD.

The “A” level is programmed by using a verify level AV which is slightlyhigher than the read level AR, and the “A” level has a higher thresholdthan the verify level AV. The “B” level is programmed by using a verifylevel BV which is slightly higher than the read level BR, and the “B”level has a higher threshold than the verify level BV. The “C” level isprogrammed by using a verify level CV which is slightly higher than theread level CR, and the “C” level has a higher threshold than the verifylevel CV.

[1-1-4] Configurations of Sense Amplifier Unit 113 and Page Buffer 115

Next, the configurations of the sense amplifier unit 113 and page buffer115 are described. FIG. 6 is a block diagram of the sense amplifier unit113 and page buffer 115.

The sense amplifier unit 113 includes sense amplifiers SA<0> to SA<L−1>which are provided in association with the bit lines BL0 to BL(L−1),respectively. Each of the sense amplifiers SA senses and amplifies datawhich was read to the corresponding bit line BL, and transfers writedata to the corresponding bit line BL.

The page buffer 115 includes, for example, three data caches LDL, UDL,and XDL. For example, the data cache LDL is used for temporarily storinga lower page, the data cache UDL is used for temporarily storing anupper page, and the data cache XDL is connected to the input/outputcircuit 119 and temporarily stores data that was sent from theinput/output circuit 119 and data that is to be sent to the input/outputcircuit 119. Specifically, even when the data caches LDL and UDL arebeing used, the page buffer 115 can receive data from the input/outputcircuit 119 by using the data cache XDL. Like the sense amplifiers SA<0>to SA<L−1>, each of the data caches LDL, UDL and XDL includes anL-number of data cache portions which are provided in association withthe bit lines BL0 to BL(L−1).

[1-1-5] Configurations of Sensor Amplifier SA and Cell Current MeasuringCircuit 40

Next, the configurations of the sense amplifier SA and a cell currentmeasuring circuit 40 are described. FIG. 7 is a circuit diagram of amain part of the sense amplifier SA and the cell current measuringcircuit 40.

First, the configuration of the sense amplifier 40 is described. Thesense amplifier SA includes a p-channel MOS transistor 31, and n-channelMOS transistors 32 to 35.

A signal VBLC is input to the gate of the transistor 35, and one end ofthe current path of the transistor 35 is connected to the correspondingbit line BL. The transistor 35 has a function of clamping thecorresponding bit line BL at a voltage corresponding to the level of thesignal VBLC. The signal VBLC is supplied from a bit line driver (BLDR)117 a which is included in the driver 117. One end of the current pathof the transistor 34 is connected to the other end of the current pathof the transistor 35, the other end of the current path of thetransistor 34 is connected to a node SEN, and a signal XXL is input tothe gate of the transistor 34.

One end of the current path of the transistor 33 is connected to theother end of the current path of the transistor 35, and a signal BLX isinput to the gate of the transistor 33. One end of the current path ofthe transistor 32 is connected to the other end of the current path ofthe transistor 33, a power supply voltage VHSA is applied to the otherend of the current path of the transistor 32, and a signal BLY is inputto the gate of the transistor 32. One end of the current path of thetransistor 31 is connected to the other end of the current path of thetransistor 33, the power supply voltage VHSA is applied to the other endof the current path of the transistor 31, and a signal INV is input tothe gate of the transistor 31. The transistors 31 and 32 constitute atransfer gate.

At a time of data read, the signals BLX and BLY are set at “H” level,the signal INV is set at “L” level, and the transfer gate (transistors31, 32) and the transistor 33 are set in the ON state. Thereby, a cellcurrent iCELL flows through the transistor 35, bit line BL and NANDstring. At this time, the ON state of the transistor 35 is controlled inaccordance with the level of the signal VBLC, and the cell current iCELLis controlled.

If data of a selected memory cell is read to the bit line BL, the signalXXL is set at “H” level, and the transistor 34 is set in the ON state.Thereby, the data, which was read to the bit line BL, is transferred tothe node SEN. Further, the data, which was transferred to the node SEN,is stored in any one of the data caches of the page buffer 115.

Next, the configuration of the cell current measuring circuit 40 isdescribed. The cell current measuring circuit 40 has a function ofkeeping the source line SL at a certain voltage. The cell currentmeasuring circuit 40 is provided for each source line SL. The cellcurrent measuring circuit 40 includes a constant-current source 41, anoperational amplifier 42, and an n-channel MOS transistor 43. Thecontrol circuit 120 may include the cell current measuring circuit 40,or a source line control circuit (not shown) may include the cellcurrent measuring circuit 40.

The constant-current source 41 supplies a constant-current iCONST to thesource line SL. The constant-current source 41 is connected between apower supply voltage VDDSA and the source line SL. The drain of thetransistor 43 is connected to the source line SL, and a ground voltageGND is applied to the source of the transistor 43. A positive inputterminal of the operational amplifier 42 is connected to the source lineSL, a reference voltage VREF is applied to a negative input terminal ofthe operational amplifier 42, and an output terminal of the operationalamplifier 42 is connected to the gate of the transistor 43. In addition,a signal GSLDRV, which is output from the output terminal of theoperational amplifier 42, is input to the control circuit 120.

In the meantime, the circuit for measuring the cell current is notlimited to the configuration of FIG. 7. For example, the circuit isdisclosed in U.S. patent application Ser. No. 13/832,983 filed on Mar.15, 2013, titled “Semiconductor memory device”. The entire contents ofthe patent application are incorporated herein by reference.

[1-2] Operation

Next, the operation of the NAND flash memory 100 with theabove-described configuration is described.

[1-2-1] Cell Current Measuring Operation

First, a cell current measuring operation is described. The cell currentmeasuring operation is included in a lower page program operation. FIG.8 is a timing chart of the lower page program operation including thecell current measuring operation. FIG. 8 illustrates waveforms of thebit line BL, source line SL, and signal GSLDRV which is output from thecell current measuring circuit 40. The cell current measuring operationis executed in a first step of the lower page program operation.

Before lower page program is executed, the memory cell transistor is inan erase state (a state in which no data is written). The controlcircuit 120 executes a read operation on a selected page that is atarget of lower page program, by using a level at which the memory celltransistor in the erase state is turned on, for example, by using theread level CR.

As illustrated in FIG. 7, the constant-current source 41 included in thecell current measuring circuit 40 supplies a constant-current iCONST tothe source line SL. Thereby, a cell current iCELL flows in the sourceline SL from the bit line BL, and the constant-current iCONST flows inthe source line SL from the constant-current source 41. On the otherhand, from the source line SL, a discharge current iSLDIS flows toward aground terminal GND via the transistor 43. Thus, the voltage of thesource line SL varies due to a balance between the incoming cell currentiCELL and constant-current iCONST and the outgoing discharge currentiSLDIS.

The magnitude of the discharge current iSLDIS is controlled by thetransistor 43. The degree of conductivity of the transistor 43 iscontrolled by the output signal GSLDRV of the operational amplifier 42.The output signal GSLDRV is an analog signal which is representative ofa comparison result between the voltage of the source line SL andreference voltage VREF by the operational amplifier 42. Accordingly, asthe voltage of the source line SL is higher, compared to the referencevoltage VREF, the value of the output signal GSLDRV becomes greater tothe positive side, the degree of conductivity of the transistor 43becomes higher, and the discharge current iSLDIS becomes larger. As aresult, the voltage of the source line SL lowers. Conversely, as thevoltage of the source line SL is lower, compared to the referencevoltage VREF, the value of the output signal GSLDRV becomes greater tothe negative side, the degree of conductivity of the transistor 43becomes lower, and the discharge current iSLDIS becomes smaller. As aresult, the voltage of the source line SL rises. In this manner, thevoltage of the source line SL continues to be constantlyfeedback-controlled in a manner to approach the reference voltage VREF.

The control circuit 120 receives the output signal GSLDRV of theoperational amplifier 42, and analog/digital (A/D) converts the outputsignal GSLDRV. Subsequently, the control circuit 120 varies a signalVBL_DAC until the signal GSLDRV becomes equal to a reference signalF_VCLAMP that is a target. The signal F_VCLAMP is stored, for example,in the register 122. The signal VBL_DAC is supplied to the bit linedriver 117 a. The bit line driver 117 a generates the signal VBLC, basedon the signal VBL_DAC, and supplies the signal VBLC to the gate of thetransistor 35 included in the sense amplifier SA. At last, an optimal(target) cell current iCELL is realized in accordance with the signalVBLC that was adjusted by the signal VBL_DAC. The signal VBL_DAC, whichwas acquired in the iCELL measuring phase and was optimized, is set asflag data in a redundancy area of the page in a program phase.

FIG. 9 is a graph for explaining an example of the relationship betweenthe signal VBLC and cell current iCELL. An abscissa in FIG. 9 indicatesthe number of times of write/erase (W/E number). In FIG. 9, “Fresh”indicates a state in which the number of times of write/erase of theNAND flash memory 100 is substantially zero, for example, a state at atime of product shipment.

In the example of FIG. 9, the target value of the cell current iCELL isabout 107 nA. In general, as the W/E number increases, the cell currentiCELL lowers. Thus, if the level of the signal VBLC is constantregardless of the W/E number, the cell current iCELL becomes large whenthe W/E number is small, that is, the current consumption increases. Onthe other hand, in the present embodiment, the cell current is measuredat a time of write, and the optimal signal VBLC is generated so that thecell current iCELL may become the target value. Thereby, the cellcurrent iCELL, in particular, at a time when the W/E number is small,can be reduced.

In the meantime, in the lower page program, an operation is executed forloading write data (lower page data) in the data cache in the pagebuffer 115 from the input/output circuit 119. Thus, the cell currentmeasuring operation in this embodiment may be executed in parallel withthe data load operation. Thereby, in the lower page program, there is noneed to newly provide a time for executing the cell current measuringoperation.

[1-2-2] Setting of Operation Parameters

As described above, as the W/E number increases, the cell current iCELLdecreases. Thus, in the present embodiment, the degree of degradation ofthe memory cell array is determined by utilizing the VBL_DAC which isused in order to control the cell current iCELL. Then, in accordancewith the determined degree of degradation of the memory cell array, theoperation parameters of the memory cell array 111 are changed.Specifically, based on the degree of degradation of the memory cellarray, the parameters of voltages, which are used for the programoperation, read operation and erase operation, are corrected.

FIG. 10 is a view illustrating a relationship between the signal VBL_DACand operation parameters. A program parameter set includes an initialprogram voltage IVPGM which is used in an initial program loop, and astep-up voltage DVPGM which increases each time a program loop isexecuted. In addition, the program parameter set may include a verifyparameter set. The verify parameter set includes a verify level and avoltage VRAED. A read parameter set includes a read level and a voltageVRAED. Various parameter sets are stored in the register 122.

The signal VBL_DAC is, for example, a 4-bit signal. At the time ofproduct shipment, it is assumed that the voltage setting (e.g. BL=0.4 V)corresponds to the signal VBL_DAC=0100 at a time of read and verify. Asthe W/E number becomes larger, the cell current decreases and the signalVBL_DAC increases. However, up to the signal VBL_DAC=0111, the sametreatment as in the fresh state is adopted and a first program parameterset is used.

At a time point when the signal VBL_DAC has reached VBL_DAC=1000, it isdetermined that the W/E number has reached 1K (1000 times), and a changeis made to a second program parameter set. In addition, at a time pointwhen the signal VBL_DAC has reached VBL_DAC=1011, it is determined thatthe W/E number has reached 2K, and a change is made to a third programparameter set. Furthermore, at a time point when the signal VBL_DAC hasreached VBL_DAC=1110, it is determined that the W/E number has reached3K, and a change is made to a fourth program parameter set.

For example, if the W/E number reaches about 3K, the write time becomesshorter (i.e. the number of program loops decreases), and the thresholddistribution becomes wider. Thus, in the fourth program parameter set,for example, the initial program voltage IVPGM and step-up voltage DVPGMare set to be low. Thereby, a threshold distribution, which is equal tothe threshold distribution in the fresh state, can be realized. Asregards the second and third program parameter sets, too, parametercorrection corresponding to the degree of degradation of the memory cellarray is executed.

FIG. 11 is a view illustrating another example of the relationshipbetween the signal VBL_DAC and operation parameters. In the example ofFIG. 11, the signal VBL_DAC is trimmed such that the cell current iCELLbecomes the target value at the time of product shipment. Although thenormal design target is the signal VBL_DAC=0100, it is assumed that thecell current iCELL reached the target value when the signalVBL_DAC=0001, due to variances in fabrication. As illustrated in FIG.11, the parameter sets, as a whole, are shifted upward by “3”. In thischip, when the signal VBL_DAC has reached VBL_DAC=0101, it is determinedthat the design target is “1K W/E”.

Incidentally, the erase parameter sets, like the program parameter sets,are changed based on the signal VBL_DAC. As illustrated in FIG. 12, inorder to change the erase parameter set, flag data corresponding to thesignal VBL_DAC is read in the erase operation. Then, based on the flagdata, the erase parameter set is changed. The erase parameter setincludes an erase voltage VERA and a WL voltage, which are used at thetime of erase, and a BL voltage and a WL voltage, which are used at thetime of erase verify.

Besides, the program parameter set, read parameter set and eraseparameter set illustrated in FIG. 10 and FIG. 11 may be changed at thesame time, or may be changed individually.

[1-2-3] Lower Page Program Operation

Next, a lower page program operation is described. FIG. 13 is aflowchart of the lower page program operation.

In a first step of the program operation, the control circuit 120executes a cell current measuring operation by using, for example, aread level CR (step S100). The cell current measuring operation is asdescribed above. In the cell current measuring operation, the controlcircuit 120 acquires a signal VBL_DAC (step S101). In addition, thecontrol circuit 120 sets the signal VBL_DAC as flag data in a redundancyarea of the page.

Subsequently, based on the signal VBL_DAC, the control circuit 120selects a program parameter set (step S102). The selection of theprogram parameter set is executed as illustrated in FIG. 10 (or FIG.11). The selected program parameter set is used through a plurality ofprogram loops.

Subsequently, the control circuit 120 determines whether the programloop number has reached a maximum value or not (step S103). If theprogram loop number has not reached the maximum value, the controlcircuit 120 executes a program operation of applying a program voltageto the selected word line (step S104). In the program operation, thecontrol circuit 120 writes user data in a normal area of the page, andsets the signal VBL_DAC, which was acquired in step S101, as flag datain the redundancy area of the page.

FIG. 14 is a view for explaining a redundancy area for writing flagdata. A page, which is composed of a plurality of memory celltransistors connected to one word line WL, includes a normal area forstoring normal data (user data), and a redundancy area. In thisembodiment, flag data is stored in the redundancy area. User data, whichis written together with the flag data, is stored in the normal area.

Subsequently, the control circuit 120 executes a verify operation ofconfirming (verifying) a threshold of the memory cell transistor (stepS105). In addition, in the verify operation, the program parameter set,which was selected in step S102, is used. Further, in the verifyoperation, the control circuit 120 adjusts the bit line voltage by usingthe VBL_DAC which was acquired in step S101. Thereby, in the verifyoperation, a cell current iCELL, which is a target, is realized.

Following the above, the control circuit 120 determines whether verifyhas been passed or not (step S106). If verify is not passed, the controlcircuit 120 steps up the program voltage by a step-up voltage DVPGM, andexecutes a program loop once again (step S107). Thereafter, theapplication of the program voltage and the verify operation are repeateduntil verify is passed.

FIG. 15 illustrates a voltage waveform of a voltage which is applied toa selected word line. An initial program voltage and a step-up voltage,which are included in the first program parameter set, are denoted byIVPGM1 and DVPGM1, respectively. In the lower page program, the verifyoperation is executed by using a verify level ML2V.

FIGS. 16A to 16D are a view for explaining an example of initial programvoltages and step-up voltages included in the first to fourth programparameter sets. FIGS. 16A to 16D correspond to the first to fourthprogram parameter sets, respectively.

In the example of FIGS. 16A to 16D, the levels of initial programvoltages IVPGM1 to IVPGM4 of the first to fourth program parameter setsbecome lower in the named order. In addition, the levels of step-upvoltages DVPGM1 to DVPGM4 of the first to fourth program parameter setsbecome lower in the named order.

[1-2-4] Upper Page Program Operation

Next, an upper page program operation is described. FIG. 17 is aflowchart of the upper page program operation. FIG. 18 is a timing chartof the upper page program operation. FIG. 18 illustrates waveforms ofthe bit line BL and source line SL.

In this embodiment, a read operation for reading flag data is includedin the upper page program operation. The flag data read operation isexecuted in a first step of the upper page program operation.

The flag data is stored in the lower page. Thus, the control circuit 120executes the flag data read operation by using the read level ARL fordetermining lower page data (step S200). Subsequently, the controlcircuit 120 acquires a signal VBL_DAC from the read flag data (stepS201). In addition, the control circuit 120 sets the signal VBL_DAC inthe redundancy area of the page as flag data.

Then, the control circuit 120 selects a program parameter set, based onthe signal VBL_DAC (step S202). The selection of the program parameterset is executed as illustrated in FIG. 10 (or FIG. 11).

Subsequently, the control circuit 120 determines whether the programloop number has reached a maximum value or not (step S203). If theprogram loop number has not reached the maximum value, the controlcircuit 120 executes a program operation of the upper page (step S204).In the upper page program, program operations of “A” level, “B” leveland “C” level are successively executed.

In the program operation, the control circuit 120 sets the flag data,which was read in step S200, in the data cache UDL, and writes the flagdata in the redundancy area as the upper page. Specifically, the flagdata of the upper page becomes identical to the flag data of the lowerpage. Thereby, the flag data after the program of the upper page becomes“11” data or “00” data. In this manner, since the thresholddistributions of the two-value data do not neighbor each other, itbecomes possible to suppress a change of data due to a thresholdvariation of the memory cell transistor MT. The subsequent operation isthe same as in the case of the lower page program.

[1-2-5] Read Operation

Next, a read operation is described. FIG. 19 is a timing chart of theread operation. In the read operation of the present embodiment, tworead operations, namely first read for reading flag data and second readfor reading normal data, are executed.

For example, upon receiving a read command, the control circuit 120outputs a busy signal. Subsequently, the control circuit 120 executesthe first read operation for flag data. The read operation of flag datais the same as, for example, the flag data read operation (step S200) ofFIG. 17.

Following the above, the control circuit 120 executes the second readoperation for reading normal data. In the second read operation, thecontrol circuit 120 executes an adjustment operation of a bit linevoltage. Thereby, in the second read operation, a cell current iCELLthat is a target is realized. Further, the control circuit 120 selects aread parameter set, based on flag data, and executes the second readoperation by using the read parameter set. A read operation, whichcorresponds to the degree of degradation of the memory cell array, canbe realized.

In the meantime, the erase parameter set, like the program parameterset, is selected based on the signal VBL_DAC. In the case of the eraseoperation, like the read operation of FIG. 19, flag data is read in thefirst step prior to the erase operation. The erase parameter setincludes an initial erase voltage IVERA and a step-up voltage DVERA. Inaddition, a voltage, which is applied to the word line at the time oferase, may be varied.

[1-3] Example of Application to Multi-Stacked Memory Cell Array

In a multi-stacked memory cell array, the diameter of a semiconductorlayer, in which channels are formed, is different between a lower partand an upper part of the NAND string. It is thus possible thatoperational characteristics are different between a memory celltransistor included in the lower part of the NAND string and a memorycell transistor included in the upper part of the NAND string. To copewith this, the NAND string is divided into some areas and managed,thereby varying operation parameters on an area-by-area basis.

FIG. 20 is a cross-sectional view for explaining areas of a NAND string.The NAND string 114 is composed of a bottom area BA, a middle area MAand a top area TA. Incidentally, the number of divided areas is merelyan example, and may arbitrarily be set. In addition, the number of wordlines included in each area (the number of memory cell transistors) isalso arbitrarily settable.

Next, the erase parameter set, which is used at the time of the eraseoperation, is described. FIG. 21 is a view illustrating the relationshipbetween the signal VBL_DAC and erase parameter sets.

As illustrated in FIG. 21, erase parameter sets are prepared for thebottom area BA, middle area MA and top area TA, respectively.

In the refresh state, first to third erase parameter sets are used forthe bottom area BA, middle area MA and top area TA, respectively. In thefirst erase parameter set, the erase voltage VERA is 20 V, and the wordline voltage at the time of erase is 0.2 V. The voltages included in thesecond to 12th erase parameter sets are as illustrated in FIG. 21.

In this manner, by changing the operation parameter sets in accordancewith the bottom area BA, middle area MA and top area TA, more optimaloperations corresponding to the respective areas can be realized.

In addition, like the erase parameters, the program parameters(including verify parameters) and read parameters can be set for thebottom area BA, middle area MA and top area TA, respectively.

In the meantime, the operation parameter sets (program parameter sets,read parameter sets and erase parameter sets) may be set more finelythan in FIG. 20, and may be set, for example, on a word line by wordline basis.

[1-4] Advantageous Effects

As has been described above in detail, in the first embodiment, in thelower page program operation, the cell current measuring operation isexecuted. In addition, based on the signal VBL_DAC acquired in the cellcurrent measuring operation, the optimal program parameter sets areselected. Thereby, a more optimal program operation and a more optimalverify operation can be realized in accordance with the degree ofdegradation of the memory cell array. Specifically, sharper thresholddistributions can be set.

Additionally, also in the read operation and erase operation, the sameadvantageous effects as in the program operation can be obtained.Thereby, a NAND flash memory 100 with high data reliability can berealized.

Additionally, in the present embodiment, by controlling the signalVBL_DAC in accordance with the degree of degradation of the memory cellarray, the cell current iCELL flowing in the NAND string can be keptsubstantially constant, regardless of the number of times of write/erase(W/E number). Thereby, the power consumption of the NAND flash memory100 can be reduced.

Additionally, the operation parameter sets are changed in associationwith the areas (e.g. bottom area BA, middle area MA and top area TA) ofthe multi-stacked memory cell array. Thereby, in the NAND flash memory100 to which the multi-stacked memory cell array is applied, the datareliability can be further enhanced.

Second Embodiment

In a second embodiment, after a bit number of specific data, which is tobe written to a sampling area of the page, is counted, a first countvalue, which was counted, is stored in a redundancy area of the page.Subsequently, when data has been read from the page, the bit number ofthe specific data in the sampling area is counted, and a second countvalue is acquired. Then, the degree of degradation of the memory cellarray is determined in accordance with the difference between the firstcount value and second count value.

[2-1] Configuration of Memory Cell Array 111

First, the configuration of a memory cell array 111 is described. FIG.22 is a block diagram illustrating, mainly, the memory cell array 111according to the second embodiment.

A page, which is composed of a plurality of memory cell transistorsconnected to one word line WL, includes a normal area for storing normaldata (user data), and a redundancy area. A sampling area is provided inan arbitrary portion of the normal area. The sampling area is used forcounting, on a kind-by-kind basis, data that is to be written to thesampling area, and for counting, on a kind-by-kind basis, data which wasread from this area. The redundancy area is used for storing, as flagdata, the bit number of the counted data.

[2-2] Outline of Data Transfer in Read Operation

Next, the outline of data transfer in the read operation is described.FIG. 23 is a timing chart of data transfer in the read operation. FIG.23 illustrates signals which are transferred between the memorycontroller 200 and NAND flash memory 100 via the NAND bus. A commandlatch enable signal CLE, an address latch enable signal ALE, a writeenable signal WEn, a read enable signal REn, and an output signal I/Oare transferred between the memory controller 200 and NAND flash memory100.

The memory controller 200 asserts the signals CLE and WEn, and sends aread command “00h” to the NAND flash memory 100. Subsequently, thememory controller 200 asserts the signal ALE and WEn, and sends addresssignals A1 to A5 to the NAND flash memory 100. Following this, thememory controller 200 asserts the signals CLE and WEn, and sends a readexecution command “30h” to the NAND flash memory 100. On the other hand,the NAND flash memory 100 responds to the signals CLE, ALE and WEn, andreceives the commands and addresses.

Subsequently, the memory controller 200 asserts the signal REn, and theNAND flash memory 100 responds to the signal REn and sends data D0, D2,D3, . . . , to the memory controller 200. Meanwhile, the memorycontroller 200 receives the data from the NAND flash memory 100.

In the above manner, data is transferred between the memory controller200 and the NAND flash memory 100. In the description below, althoughthe signals CLE, ALE, WEn and REn are omitted, FIG. 23 is to be referredto in connection with the timings of these signals.

[2-3] Program Operation

Next, a program operation is described.

[2-3-1] Lower Page Program Operation

First, a lower page program operation is described. FIG. 24 is aflowchart of the lower page program operation.

The control circuit 120 loads data (lower page data), which theinput/output circuit 119 received, in the page buffer 115 (step S300).Specifically, the control circuit 120 stores the data, which was sentfrom the input/output circuit 119, in the data cache XDL, and transfersthe data from the data cache XDL to the data cache LDL.

Subsequently, using the data stored in the data cache, the controlcircuit 120 counts the bit number of “LM” level of the data written tothe sampling area (step S301). The threshold distribution of “LM” levelcorresponds to data “0”. Thereby, the number of memory cells, which areprogrammed to “LM” level (data “0”), is calculated. In addition, thecontrol circuit 120 sets the count value as flag data in the redundancyarea of the selected page.

Then, the control circuit 120 determines whether or not the program loopnumber has reached the maximum value (step S302). If the program loopnumber has not reached the maximum value, the control circuit 120executes a program operation on the selected page (step S303).

Subsequently, the control circuit 120 executes a verify operation (stepS304). Then, the control circuit 120 determines whether verify has beenpassed or not (step S305). If verify has not been passed, the controlcircuit 120 steps up the program voltage by the step-up voltage DVPGM,and executes the program loop once again (step S306).

By this operation, the number of memory cells, which are to be set inthe threshold distribution of “LM” level, among the memory cellsincluded in the sampling area, is written as flag data to the redundancyarea. Incidentally, the bit number of “E” level of the data written tothe sampling area may be counted. In this case, the number of memorycells, which are to be set in the threshold distribution of “E” level,among the memory cells included in the sampling area, is written as flagdata to the redundancy area. Then, the count value of memory cells of“E” level is used in order to determine the degree of degradation of thememory cell array.

[2-3-2] Upper Page Program Operation

Next, an upper page program operation is described. FIG. 25 is aflowchart of the upper page program operation.

The control circuit 120 loads data (upper page data), which theinput/output circuit 119 received, in the page buffer 115 (step S400).Specifically, the control circuit 120 stores the data, which was sentfrom the input/output circuit 119, in the data cache XDL, and transfersthe data from the data cache XDL to the data cache UDL. Lower page data,which is necessary for upper page program, is read from the memory cellarray in advance, and stored in the data cache LDL.

Subsequently, using the data stored in the data cache, the controlcircuit 120 counts the bit numbers of “E” level, “A” level, “B” leveland “C” level (step S401). In addition, the control circuit 120 sets thecount values as flag data in the redundancy area of the selected page.

Then, the control circuit 120 determines whether or not the program loopnumber has reached the maximum value (step S402). If the program loopnumber has not reached the maximum value, the control circuit 120executes a program operation on the selected page (step S403).

Subsequently, the control circuit 120 executes a verify operation (stepS404). Then, the control circuit 120 determines whether verify has beenpassed or not (step S405). If verify has not been passed, the controlcircuit 120 steps up the program voltage by the step-up voltage DVPGM,and executes the program loop once again (step S406). Incidentally, theprogram operation of step S403 and the verify operation of step S404include program operations and verify operations of “A” level, “B” leveland “C” level.

By this operation, the bit numbers of “E” level, “A” level, “B” leveland “C” level of the memory cells included in the sampling area arewritten as flag data to the redundancy area. In the meantime, there isno need to count the bit numbers of all levels and write the countresults to the redundancy area. It is possible to adopt such a method ascounting only “E” level and estimating, based on this, the degree ofdegradation of the other levels.

[2-4] Read Operation

Next, a read operation is described.

[2-4-1] Example 1

First, a lower page read operation is described. FIG. 26 is a flowchartof the lower page read operation according to Example 1. FIG. 27 is atiming chart of the lower page read operation according to Example 1.

The control circuit 120 receives a prefix command Prefix-CMD1, a readcommand “00h”, address signals A1 to A5, and a read execution command“30h” from the memory controller 200 (step S500). By first issuing theprefix command Prefix-CMD1, a special read mode, which is different froma mode of a normal read command, can be designated. Responding to this,the control circuit 120 sends a busy signal to the memory controller200.

Subsequently, the control circuit 120 executes a normal read operation(step S501). FIG. 28 illustrates voltage waveforms in read operations.In FIG. 28, SGD_SEL and SGS_SEL are select gate lines included in aselected string unit, and SGD_USEL and SGS_USEL are select gate linesincluded in a non-selected string unit. WL_SEL is a selected word line,and WL_USEL is non-selected word lines.

In a normal read operation, the row decoder 112 applies a voltage Vsg tothe select gate lines SGD_SEL and SGS_SEL in the selected string unit,and turns on the select transistors ST1 and ST2. In addition, the rowdecoder 112 applies a read voltage Vcgrv to the selected word lineWL_SEL, and applies a voltage VREAD to the non-selected word linesWL_USEL. Further, the row decoder 112 applies a voltage VSS (0 V) to theselect gate lines SGD_USEL and SGS_USEL in the non-selected string unit,and turns off the select transistors ST1 and ST2. Incidentally, in thecase of lower page read, the read voltage Vcgrv corresponds to the levelBR which can determine “1” and “0” of lower data.

In the normal read operation, flag data stored in the redundancy area isread, and the control circuit 120 acquires the flag data (step S502).Then, using the flag data, the control circuit 120 calculates the bitnumber of “LM” level at the time of program. Subsequently, the controlcircuit 120 transfers the data, which was read in the normal readoperation, from the sense amplifier SA to the data cache XDL. Thereby,data-out of normal read becomes possible, and the control circuit 120sends a ready signal (cache ready) to the memory controller 200 (stepS503).

Then, using the read data stored in the data cache UDL, the controlcircuit 120 counts the bit number of “LM” level in the sampling area(step S504). Subsequently, the control circuit 120 compares an expectedvalue, which was calculated from the flag data of step S502, and a readresult of step S504. Then, the control circuit 120 calculates a readlevel, based on the comparison result (step S505). In a method ofadjusting the read level, for example, as described in the firstembodiment, a plurality of read parameter sets are stored in theregister 122, and any one of the read parameter sets is selected inaccordance with the magnitude of the comparison result.

Subsequently, using the adjusted read level, the control circuit 120executes a correction read operation (step S506). Specifically, asillustrated in FIG. 28, the read operation is executed by adjusting theread voltage Vcgrv by a voltage Δ. Then, the control circuit 120transfers the data, which was read in the correction read operation,from the sense amplifier SA to the data cache LDL. Thereafter, thecontrol circuit 120 sends a ready signal (true ready) to the memorycontroller 200.

Then, the memory controller 200 sends a status read command “70h” to theNAND flash memory 100. Responding to the status read command “70h”, theNAND flash memory 100 sends a status to the memory controller 200. Bythis status, the memory controller 200 can obtain information ofcorrection read.

Subsequently, the control circuit 120 monitors whether a transfercommand “3Fh” has been received from the memory controller 200 (stepS507). If the transfer command “3Fh” has been received, the controlcircuit 120 transfers the data from the data cache LDL to the data cacheXDL (step S508). Thereafter, the control circuit 120 becomes able toexecute data-out of correction read, and the control circuit 120 sends aready signal (true ready) to the memory controller 200 (step S509).

In the meantime, in step S507, when the transfer command “3Fh” is notreceived from the memory controller 200, that is, when the normal readended normally, the data-out of correction read is not executed.

<Upper Page Read Operation>

Next, an upper page read operation is described. FIG. 29 is a flowchartof the upper page read operation.

In the upper page read operation, the control circuit 120 calculates thebit numbers of “E” level, “A” level, “B” level and “C” level, by usingthe flag data acquired in step S602.

In addition, the control circuit 120 counts the bit numbers of “E”level, “A” level, “B” level and “C” level in the sampling area, by usingthe read data stored in the data cache XDL (step S604). Thereafter, thecontrol circuit 120 calculates a read level, based on the comparisonresult (step S605).

The operation other than the above is the same as the above-describedupper page read operation. Thereby, a more precise read operation of theupper page can be realized.

<Example of Correction Value of Read Level>

Next, an example of the correction value of the read level is described.FIG. 30 is a view illustrating the relationship between a differencebetween flag data and a count value, on one hand, and read levels, onthe other hand.

As is understood from FIG. 5, the read level AR is used in order todetermine the “E” level, and the “A”, “B” and “C” levels. The read levelBR is used in order to determine the “LM” level in the lower pageprogram. The read level CR is used in order to determine the “E”, “A”and “B” levels, and the “C” level. Specifically, the read level BR isused in the lower page read operation, and the read levels AR and CR areused in the upper page read operation.

As illustrated in FIG. 30, as regards the read level AR, if thedifference in number of “E” cells is negative (the flag data issmaller), there are a large number of memory cells whose thresholdslowered to “E” level from “A”, “B” and “C” levels. It is thus necessaryto lower the read level AR.

As regards the read level BR, if the difference in number of “LM” cellsis negative (the flag data is smaller), there are a large number ofmemory cells whose thresholds rose to “LM” level. In this case, the readlevel BR needs to be raised.

As regards the read level CR, if the difference in number of “C” cellsis negative (the flag data is smaller), there are a large number ofmemory cells whose thresholds rose to “C” level from from “E”, “A” and“B” levels. In this case, the read level AR needs to be raised.

By adjusting the read level as illustrated in FIG. 30, a more preciseread operation can be realized in accordance with the degree ofdegradation of the memory cell array.

Incidentally, like the first embodiment, when the multi-stacked memorycell array is adopted, correction values may be set for the bottom areaBA, middle area MA and top area TA, respectively. Furthermore, thecorrection value may be set on a word line by word line basis.

[2-4-2] Example 2

Next, a read operation according to Example 2 is described. FIG. 31 is atiming chart of the read operation according to Example 2. FIG. 31 iscommon to a lower page read operation and an upper page read operation.

The control circuit 120 receives a prefix command Prefix-CMD2, a readcommand “00h”, address signals A1 to A5, and a read execution command“30h” from the memory controller 200. By the prefix command Prefix-CMD2,a read mode, which is different from Example 1, can be designated.

Subsequently, the control circuit 120 successively executes a normalread operation and a correction read operation. The normal readoperation and correction read operation are the same as in Example 1.Subsequently, the control circuit 120 outputs data, which was read bythe correction read operation, to the memory controller 200.

The read operation according to Example 2 is particularly effective, forexample, when page data are successively read. Specifically, when it canbe determined that the memory cell array deteriorates to some degree ina previous read operation, read data based on correction read isrequested from the beginning. Thereby, the read operation can be madesimpler than in Example 1.

[2-4-3] Example 3

Next, a read operation according to Example 3 is described. FIG. 32 is aflowchart of a lower page read operation according to Example 3. FIG. 33illustrates voltage waveforms in the lower page read operation accordingto Example 3. The timing chart of the read operation is the same as FIG.31.

The control circuit 120 receives a prefix command Prefix-CMD2, a readcommand “00h”, address signals A1 to A5, and a read execution command“30h” from the memory controller 200 (step S700). Responding to this,the control circuit 120 sends a busy signal to the memory controller200.

Subsequently, the control circuit 120 executes a normal read operation(step S701). In the normal read operation, the flag data stored in theredundancy area of the selected page is read, and the control circuit120 acquires the flag data (step S702). Then, by using the flag data,the control circuit 120 calculates the bit number of “LM” level at atime of program.

Following the above, using the read data stored in the data cache XDL,the control circuit 120 counts the bit number of “LM” level in thesampling area (step S703). Then, the control circuit 120 compares anexpected value, which was calculated from the flag data of step S702,and a read result of step S703, and determines that read has beenpassed, if the difference between the read result and the expected valuefalls within an allowable value (step S704). Thereafter, the controlcircuit 120 executes data-out of normal read.

On the other hand, if read is not passed in step S704, the controlcircuit 120 calculates a read level, based on the comparison result(step S705). In the example of FIG. 33, a read level “Vcgrv+Δ1”, inwhich a step-up voltage Δ1 is added to a normal read level Vcgrv, iscalculated.

Subsequently, the control circuit 120 determines whether the read loopnumber has reached a maximum value or not (step S706). If the read loopnumber has not reached the maximum value, the control circuit 120executes a correction read operation by using the read level “Vcgrv+Δ1”(step S707).

Then, the control circuit 120 counts the bit number of “LM” level in thesampling area included in the data that was read by the correction read(step S708). Subsequently, the control circuit 120 compares the expectedvalue, which was calculated from the flag data of step S702, and a readresult of step S708. Then, the control circuit 120 determines that readhas been passed, if the read result and expected value become equal, orthe difference between the read result and the expected value fallswithin an allowable value (step S709). Subsequently, the control circuit120 outputs to the memory controller 200 the data read by the correctionread operation (the data stored in the data cache XDL).

On the other hand, if the read fails to be passed in step S709, thecontrol circuit 120 steps up the read level by voltage Δ1 (step S710),and repeats the correction read operation. In addition, if the read loopnumber has reached the maximum value in step S706, the control circuit120 outputs the latest read data to the memory controller 200.

Incidentally, as regards the upper page read operation, the flow chartof FIG. 32 can be referred to, except that the calculation of the “LM”level of the lower page read operation is executed at each of the the“E” level, “A” level, “B” level and “C” level.

[2-5] Advantageous Effects

As has been described above in detail, according to the secondembodiment, the NAND flash memory 100 can output data with higherreliability to the memory controller 200. Conventionally, the memorycontroller 200 repeats a sequence of executing error correction of aread result from the NAND flash memory 100, and executing re-read in acase of correction NG by varying the read level. If this sequent isused, the read time increases. However, in the present embodiment, datawith higher reliability can be output to the memory controller 200, andthe read time can be reduced.

In addition, the read level is adjusted in accordance with thedifference between the flag data and the read result. Thereby, a moreoptimal read operation can be realized in accordance with degree ofdegradation of the memory cell array. As a result, the NAND flash memory100 with high data reliability can be realized. As regards the upperpage, the same advantageous effects as with the lower page can beobtained.

Furthermore, in accordance with the instruction from the memorycontroller 200, either the read data by normal read that is the firstread, or the read data by correction read that is the second andsubsequent read, can selectively be sent to the memory controller 200.Thereby, the NAND flash memory 100, which can output data that is suitedto the demand of the memory controller 200, can be realized.

Third Embodiment

In the second embodiment, bit count is executed in the NAND flash memory100, and write time increases by a degree corresponding to the bit countoperation. In a third embodiment, bit count is executed by the memorycontroller 200, and management of flag data is executed by the NANDflash memory 100.

[3-1] Write Operation

A write operation according to the third embodiment is described. FIG.34 is a timing chart illustrating a write operation of the memorycontroller 200 and NAND flash memory 100 according to the thirdembodiment. FIG. 35 is a flowchart illustrating the write operation ofthe memory controller 200 and NAND flash memory 100.

First, the memory controller 200 receives a write instruction from thehost device 400 (step S800). Subsequently, responding to the writeinstruction from the host device 400, the memory controller 200 issues awrite command “80” and an address to the NAND flash memory 100 (stepS801). Responding to the write command from the memory controller 200,the NAND flash memory 100 starts write preparation (S802).

Then, the memory controller 200 determines whether or not to execute abit count mode for comparing the bit number of data written to thesampling area and the expected value (step S803). When the bit countmode is not executed, the memory controller 200 executes a normal writeoperation. Specifically, the memory controller 200 inputs data to theNAND flash memory 100 (step S804). Responding to this, the NAND flashmemory 100 sets the data in the data cache XDL (step S805).Subsequently, the memory controller 200 issues a write execution command“15/10” to the NAND flash memory 100 (step S806). Responding to this,the NAND flash memory 100 executes write (step S807).

If the bit count mode is executed in step S803, the memory controller200 counts the bit number of a corresponding write level of the datawritten to the sampling area (step S808). Specifically, in the case oflower page program, the bit number of “LM” level (or “E” level) iscounted. In the case of upper page program, the bit number of each of“E” level, “A” level, “B” level and “C” level is counted. The bit countoperation is the same as in the second embodiment. Subsequently, thememory controller 200 sets the count value in step S808 in a countregister (step S809). The count register may be constituted by using apart of the RAM 240, or a dedicated register may be prepared.

Subsequently, the memory controller 200 inputs data to the NAND flashmemory 100 (step S810). Responding to this, the NAND flash memory 100sets the data in the data cache XDL (step S811). Then, the memorycontroller 200 issues to the NAND flash memory 100 a command “1X”notifying the end of data input (step S812). Responding to the command“1X”, the NAND flash memory 100 starts preparation for setting the countvalue in the flag (step S813). Specifically, the NAND flash memory 100transfers the data of the data cache XDL to the data cache UDL (“X2U” inFIG. 34).

Subsequently, the memory controller 200 sends the count value (CNTresult), which is stored in the count register, to the NAND flash memory100 (step S814). Then, the NAND flash memory 100 sets the count value inthe flag (step S815).

Following the above, the memory controller 200 issues a write executioncommand “15/10” to the NAND flash memory 100 (step S816). Responding tothis, the NAND flash memory 100 executes write (step S817).Specifically, as illustrated in FIG. 34, write (program) and verify(pvfy) are repeated. Thereby, the flag data corresponding to the countvalue is written to the redundancy area of the selected page.

[3-2] Read Operation

Next, a read operation according to the third embodiment is described.FIG. 36 and FIG. 37 are flowcharts illustrating the read operation ofthe memory controller 200 and NAND flash memory 100.

First, the memory controller 200 receives a read instruction from thehost device 400 (step S900). Then, responding to the read instructionfrom the host device 400, the memory controller 200 issues a readcommand and an address to the NAND flash memory 100 (step S901).Responding to the read command from the memory controller 200, the NANDflash memory 100 starts read preparation (step S902).

Subsequently, the memory controller 200 issues a read execution commandto the NAND flash memory 100 (step S903). Responding to the readexecution command, the NAND flash memory 100 starts read (step S904).

Following the above, the memory controller 200 issues a status readcommand to the NAND flash memory (step S905). Responding to the statusread command, the NAND flash memory 100 sends a status relating to readdata to the memory controller 200, and sends a ready signal to thememory controller 200 (step S906).

Subsequently, the memory controller 200 instructs data output (stepS907). Responding to this instruction, the NAND flash memory 100 outputsdata to the memory controller 200 (step S908).

Then, the memory controller 200 determines whether or not to execute thebit count mode (step S909). When the bit count mode is not executed, theerror correction of the read data is executed, and the read operationends.

If the bit count mode is executed in step S909, the memory controller200 counts, with use of the read data, the bit number of a correspondinglevel of the data of the sampling area (step S910). The bit countoperation is the same as in the second embodiment. Then, the memorycontroller 200 sets the count value of step S910 in the count register(step S911).

Subsequently, the ECC circuit 250 executes error correction of the readdata (step S912). If the error correction was normally executed (stepS913), the read operation ends. On the other hand, if the errorcorrection was not normally executed, the memory controller 200 issues,through step S914, a flag output command, which instructs output of flagdata, to the NAND flash memory 100 (step S915). Responding to the flagoutput command, the NAND flash memory 100 sends flag data to the memorycontroller 200 (step S916). Then, the memory controller 200 compares theflag data and the count value stored in the count register, andcalculates the read level, based on the comparison result (step S917).

Following the above, the memory controller 200 issues a shift readcommand, which instructs correction read (instructs a read level fromthe outside), to the NAND flash memory 100, and sends the read level instep S917 to the NAND flash memory 100 (step S918). Responding to theshift read command from the memory controller 200, the NAND flash memory100 starts read preparation (step S919).

Subsequently, the memory controller 20 issues a read command and anaddress to the NAND flash memory 100 (step S920). Then, the memorycontroller 200 issues a read execution command to the NAND flash memory100 (step S921). Thereafter, the NAND flash memory 100 executescorrection read (step S922). The correction read operation is the sameas in the second embodiment.

[3-3] Advantageous Effects

According to the third embodiment, the bit count operation can beexecuted in the memory controller 200, and the count result can bemanaged in the NAND flash memory 100. Thereby, since the NAND flashmemory 100 does not need to include a counter for the bit countoperation, the circuit size of the NAND flash memory 100 can be reduced,and the processing load of the NAND flash memory 100 can be decreased.Furthermore, the write time of the NAND flash memory 100 can bedecreased. The other advantageous effects are the same as in the secondembodiment.

Fourth Embodiment

A fourth embodiment is a modification of the third embodiment. In thefourth embodiment, the memory controller 200 executes bit count, andmanagement of flag data.

[4-1] Write Operation

A write operation according to the fourth embodiment is described. FIG.38 is a timing chart illustrating a write operation of the memorycontroller 200 and NAND flash memory 100 according to the fourthembodiment. FIG. 39 is a flowchart illustrating the write operation ofthe memory controller 200 and NAND flash memory 100.

Steps S1000 to S1002 of FIG. 39 are identical to steps S800 to S802 ofFIG. 35. Then, the memory controller 200 determines whether or not toexecute the bit count mode (step S1003). When the bit count mode is notexecuted, the memory controller 200 executes a normal write process.Specifically, the memory controller 200 inputs data to the NAND flashmemory 100 (step S1007). Responding to this, the NAND flash memory 100sets the data in the data cache XDL (step S1008). Subsequently, thememory controller 200 issues a write execution command “15/10” to theNAND flash memory 100 (step S1009). Responding to this, the NAND flashmemory 100 executes write (step S1010).

If the bit count mode is executed in step S1003, the memory controller200 counts the bit number of a corresponding write level of the datawritten to the sampling area (step S1004). Subsequently, the memorycontroller 200 sets the count value in step S1004 in the count register(step S1005).

Then, the memory controller 200 associates the write level and countvalue and stores the associated write level and count value in the RAM240 (step S1006). Subsequently, the above-described steps S1007 to S1010are executed.

[4-2] Read Operation

Next, a read operation according to the fourth embodiment is described.FIG. 40 is a flowchart illustrating the read operation of the memorycontroller 200 and NAND flash memory 100. Steps S900 to S914 in thefourth embodiment are identical to steps S900 to S914 (FIG. 36 and FIG.37) described in the read operation of the third embodiment. FIG. 40shows a flowchart of step S913 or later.

If the bit count mode is executed in step S914, the memory controller200 compares the count value, which was stored in the count register instep S911, and the count value stored in the RAM 240 in step S1006 (stepS1100). Then, the memory controller 200 calculates the read level, basedon the comparison result of step S1100 (step S1101).

Subsequently, the memory controller 200 issues a shift read command tothe NAND flash memory 100, and sends the read level in step S1101 to theNAND flash memory 100 (step S1102). The subsequent steps S1103 to S1106are identical to steps S919 to S922 of the third embodiment.

[4-3] Advantageous Effects

According to the fourth embodiment, the bit count operation and themanagement of the count result can be executed in the memory controller200. Thereby, since the NAND flash memory 100 does not need to store thecount value, the processing load of the NAND flash memory 100 can bedecreased. Furthermore, the write time of the NAND flash memory 100 canbe decreased. The other advantageous effects are the same as in thesecond embodiment.

In the embodiments according to the present invention:

(1) The voltage applied to the word line selected for the read operationat the “A”-level may be, for example, 0 V to 0.55 V. The voltage is notlimited thereto, and may be 0.1 V to 0.24 V, 0.21 V to 0.31 V, 0.31 V to0.4 V, 0.4 V to 0.5 V, or 0.5 V to 0.55 V.

The voltage applied to the word line selected for the read operation atthe “B”-level is, for example, 1.5 V to 2.3 V. The voltage is notlimited thereto, and may be 1.65 V to 1.8 V, 1.8 V to 1.95 V, 1.95 V to2.1 V, or 2.1 V to 2.3 V.

The voltage applied to the word line selected for the read operation atthe “C”-level is, for example, 3.0 V to 4.0 V. The voltage is notlimited thereto, and may be 3.0 V to 3.2 V, 3.2 V to 3.4 V, 3.4 V to 3.5V, 3.5 V to 3.6 V, or 3.6 V to 4.0 V.

The time (tR) for the read operation may be, for example, 25 μs to 38μs, 38 μs to 70 μs, or 70 μs to 80 μs.

(2) The write operation includes the program operation and theverification operation as described above. In the write operation, thevoltage first applied to the word line selected for the programoperation may be, for example, 13.7 V to 14.3 V. The voltage is notlimited thereto, and may be 13.7 V to 14.0 V or 14.0 V to 14.6 V.

The voltage first applied to the selected word line in the writing intoan odd word line, and the voltage first applied to the selected wordline in the writing into an even word line may be changed.

When the program operation is an incremental step pulse program (ISPP)type, a step-up voltage is, for example, about 0.5.

The voltage applied to the unselected word line may be, for example, 6.0V to 7.3 V. The voltage is not limited thereto, and may be, for example,7.3 V to 8.4 V or may be 6.0 V or less.

The pass voltage to be applied may be changed depending on whether theunselected word line is an odd word line or an even word line.

The time (tProg) for the write operation may be, for example, 1700 μs to1800 μs, 1800 μs to 1900 μs, or 1900 μs to 2000 μs.

(3) In the erase operation, the voltage first applied to a well which isformed on the semiconductor substrate and over which the memory cellsare arranged may be, for example, 12 V to 13.6 V. The voltage is notlimited hereto, and may be, for example, 13.6 V to 14.8 V, 14.8 V to19.0 V, 19.0 to 19.8 V, 19.8 V to 21 V.

The time (tErase) for the erase operation may be, for example, 3000 μsto 4000 μs, 4000 μs to 5000 μs, or 4000 μs to 9000 μs.

(4) The structure of the memory cell may have the charge storage layerdisposed on the semiconductor substrate (silicon substrate) via a tunnelinsulating film having a thickness of 4 to 10 nm. This charge storagelayer may have a stacked structure including an insulating film of SiNor SiON having a thickness of 2 to 3 nm and polysilicon having athickness of 3 to 8 nm. A metal such as Ru may be added to polysilicon.An insulating film is provided on the charge storage layer. Thisinsulating film has, for example, a silicon oxide film having athickness of 4 to 10 nm intervening between a lower high-k film having athickness of 3 to 10 nm and an upper high-k film having a thickness of 3to 10 nm. The high-k film includes, for example, HfO. The silicon oxidefilm can be greater in thickness than the high-k film. A controlelectrode having a thickness of 30 to 70 nm is formed on the insulatingfilm via a material for work function adjustment having a thickness of 3to 10 nm. Here, the material for work function adjustment includes ametal oxide film such as TaO or a metal nitride film such as TaN. W, forexample, can be used for the control electrode.

An air gap can be formed between the memory cells.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A semiconductor memory device comprising: amemory cell array including memory strings, one of the memory stringsincluding memory cells; word lines commonly connected to the memorystrings; and a controller configured to execute a write operation and aread operation on a page, the page being stored in memory cellsconnected to one of the word lines, wherein the controller is configuredto: count a bit number of a first level which is to be written to asampling area, which is a part of the page, to obtain a first countvalue, and write the first count value to a redundancy area of the page,read, in a first read, the first count value from the redundancy area,and count a bit number of the first level which was read from thesampling area, to obtain a second count value, and adjust, in a secondread, a read voltage applied to a word line, based on a differencebetween the first count value and the second count value.
 2. The deviceof claim 1, further comprising: a first data cache configured to storeread data by the first read; and a second data cache configured to storeread data by the second read, wherein the controller is configured tooutput either the data of the first data cache or the data of the seconddata cache in accordance with a command received from an outside.
 3. Thedevice of claim 1, further comprising: a first data cache configured tostore read data by the first read; and a second data cache configured tostore read data by the second read, wherein the controller is configuredto output the data of the first data cache at a first timing, and outputthe data of the second data cache when a command is received from anoutside at a second timing.
 4. The device of claim 1, further comprisinga data cache configured to store write data received from an outside,wherein the controller is configured to count the bit number of thefirst level by using the write data stored in the data cache.
 5. Thedevice of claim 1, further comprising a register configured to storeparameters including information of the read voltage, wherein thecontroller is configured to: select one of the parameters, based on thedifference the first count value and the second count value, anddetermine the read voltage by using the selected parameter.
 6. Thedevice of claim 1, wherein the controller is configured to set the readvoltage in the second read to be higher than a read voltage in the firstread.
 7. The device of claim 1, wherein the controller is configured tostep up the read voltage and repeat the read operation, when thedifference between the first count value and the second count value isgreater than a threshold.
 8. A semiconductor memory device comprising:memory strings, each of the memory strings including a plurality ofmemory cells; a word line electrically connected to a plurality of firstmemory cells, each of the plurality of first memory cells being includedin a corresponding one of the memory strings, the plurality of firstmemory cells being capable of storing first data and second data, thefirst data corresponding to a first page, the second data correspondingto a second page; and a controller configured to execute a writeoperation and a read operation on a page, wherein the controller isconfigured to: measure a cell current flowing in a memory string in afirst write operation on the word line for writing the first data to theplurality of first memory cells, and adjust a write voltage applied tothe word line in a second write operation for writing the second data tothe plurality of first memory cells, based on a measurement result ofthe cell current.
 9. The device of claim 8, wherein the controller isconfigured to: write the measurement result to a redundancy area of thefirst page, read the measurement result from the redundancy area in afirst read, and adjust, in a second read, a read voltage applied to theword line, based on the measurement result.
 10. The device of claim 8,wherein the controller is configured to: write the measurement result ina redundancy area of the first page, read the measurement result fromthe redundancy area, and adjust the write voltage applied to the wordline, based on the measurement result.
 11. The device of claim 10,wherein the write voltage is set to become smaller as the cell currentbecomes smaller.
 12. The device of claim 10, wherein in an eraseoperation, the controller is configured to: read the measurement resultfrom the redundancy area, and adjust an erase voltage, based on themeasurement result.
 13. The device of claim 12, wherein the erasevoltage is set to become larger as the cell current becomes smaller. 14.The device of claim 8, further comprising a register configured to storeparameters including information of the write voltage, wherein thecontroller is configured to: select one of the parameters, based on themeasurement result, and determine the write voltage by using theselected parameter.
 15. The device of claim 8, wherein the memory cellsare stacked and comprise a first group and a second group which aredivided along a direction of the stacking, and the controller isconfigured to further adjust the write voltage in accordance with thefirst group and the second group.
 16. The device of claim 8, wherein thecontroller is configured to: write the measurement result in aredundancy area of the first page, and adjust a read voltage applied tothe word line in the read operation, based on the measurement result.